info@highX-tech.com
Library of highly configurable Behavioral IPs
optimized for High-Level Synthesis (ANSI C and SystemC)
Need to learn about HLS and if the technology can be applied to your designs?
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Patent searches and expert witness.
Design and customization of behavioral IPs
ASICs and FPGAs
Converting legacy synthesizable RTL code (Verilog or VHDL) into synthesizable
code optimized for High-Level Synthesis
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.FIR Filter (configurable number of taps)
Interpolation Filter (configurable number of stages
Decimation Filter (configurable number of stages)
FFT (configurable number points)
Cholesky decomposition
AES (cipher, decipher, multiple modes and IOs)
kasumi
snow3G
m5dc
sha
ANNs (Auto-encoder, hand-written digits recognition,etc.)
sobel
JPEG encoder, decoder
Viola-Jones face detection
VGA controller
adpcm
UART
Viterbi decoder
MIPS (scalar)
MIPS (pipelined)
RISC-V (pipelined)
highX technologies was founded in 2023 by Prof. Carrion Schaefer who has over 20 years of academic and industrial experience in the design of hardware systems, FPGA and ASICs as well as in the development of commercial HLS tools. From 2007 to 2012 he was a member of the NEC teams that developed NEC's HLS tool CyberWorkbench.
Prof. Carrion Schaefer also served multiple years at OSCI's (now Accellera's) SystemC synthesizable subset working group as one of the members drafting the latests draft (version 1.3).
Prof. Carrion Schaefer, holds a Ph.D. from The University of Birmingham, UK and an MBA from McGill University, Canada. He currently serves as associate Professor at The University of Texas at Dallas at the department of Electrical and Computer Engineering (ECE) where he has established the Design and Reconfigurable Computing Laboratory (DARClab).
UT Dallas, incubator hub
800 W Campbell Road, Richardson, TX, 75080 info@highX-tech.com